MSP430 Instruction Set Architecture ! MSP430 CPU specifically designed to allow the use of modern programming techniques, such as: - the computation of jump addresses - data processing in tables - use of high-level languages such as C. ! 64KB memory space with 16 16-bit registers that reduce fetches to memory. ! 4 0856H-AVR-07/09 AVR Instruction Set I/O Direct Figure 3. I/O Direct Addressing Operand address is contained in 6 bits of the instructio n word. n is the destination or source register address. 5. 5(6) means: 5 cycles if branch not taken, 6 cycles if taken (Branch instructions. 6. SWI sets I and F bits. SW12 and SW13 do not affect I and F. 7. Conditions Codes set as a direct result of the instruction. 8. Value of half carry flag is undefined. 9. Special Case Carry set if b7 is SET. The PowerPC e600 is a family of 32-bit Power Architecture microprocessor cores developed by MPC8640D MPC8640: 90 nm SOI: 225 M: 177.87 silicon in October 1992 The PowerPC 601 was the first generation of microprocessors to support the basic 32-bit PowerPC instruction set . The design — Two separate 32-Kbyte instruction and data level 1 (L1) caches — Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cache with ECC — 36-bit real addressing — Separate memory management units (MMUs) for instructions and data — Multiprocessing support features — Power and thermal management MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications 1 Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B, 2C & 2D): Instruction Set Reference, A-Z NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of three volumes: MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 3 Overview 1.1 Key Features The following lists the MPC8640 key feature set: † Major features of the e600 core are as follows: — High-performance, 32-bit superscalar microprocessor that implements the PowerPC instruction set architecture (ISA) Comp 411 L03 -Instruction Set 3 A General-Purpose Computer The von Neumann Model Many architectural approaches to the general purpose computer have been explored. Search among more than 1.000.000 user manuals and view them online in .pdf MPC5553/MPC5554 Microcontroller Reference Manual Devices Supported: MPC5553 MPC5554 MPC5553/4RM Rev. 3.1 10/2005. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are The MPC8640 integrates one e600 core while the MPC8640D integrates two cores. This section provides a high-level overview of the MPC8640 and MPC8640D features. (L1) caches Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cache with ECC 36-bit real The MPC8640 integrates one e600 core while the MPC8640D integrates two cores. This section provides a high-level overview of the MPC8640 and MPC8640D features. (L1) caches Integrated 1-Mbyte, eight-way set-associative unified instruction and data level 2 (L2) cache with ECC 36-bit real The result was the POWER instruction set architecture, introduced with the RISC System/6000 in early 1990, the original POWER microprocessor, one of the first superscalar RISC implementations, was a high performance, multi-chip design. implements the PowerPC™ instruction set architecture version 1.0 and is targeted at networking and computing systems applications. The MPC7448 consists of a processor Hardware Specifications.