Tradeoff between Data-, Instruction-, and Thread-Level Parallelism in Stream Processors Jung Ho Ahn Hewlett-Packard Laboratories Palo Alto, California model [16] and not for programs that feature only instruction-level parallelism or that rely on ?ne-grained interacting threads. Instruction-Level Parallelism and Its Exploitation 2 Introduction Instruction-Level Parallelism Basics Control stalls Fundamental unit for extracting parallelism is -Basic block (block of instructions between branches) fact, cannot convey any explicit information regarding parallelism. Since the program contains no explicit information regarding the dependences between the instructions, if instruction-level parallelism is to be employed, the dependences that exist must be determined by the hardware, which must then make the scheduling decisions as well. difference between the BBV obtained for the first 100. Instruction level parallelism become more of a problem, since there are even fewer clock cycles between branches. Instruction-level parallelism exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping. Machine Parallelism - The measure of the ability of the processor to take advantage of instruction-level parallelism. This instruction level parallelism exploited within each thread allows decrease in running times with increasing number of threads far beyond the number of physical cores. A load-balanced scheme is introduced that allows effcient comparisons between spectra on multiple cores. View Slot27-CH16-ParallelismSuperScalar-22-slides.pptx from CEA 210 at FPT University. + Chapter 16 Instruction-Level Parallelism and Superscalar Processors William Stallings, Computer Organization What is instruction level parallelism? Execute independent instructions in parallel • Provide more hardware function units (e.g., adders, cache ports) • Detect instructions that can be executed in parallel (in hardware or software) • Schedule in